Level shifter circuit

ABSTRACT

Embodiments of the present invention provide a level converter circuit with a resistor and a current adjustment circuit. The resistor is connected between an input and an output of the level converter circuit. The current adjustment circuit is configured to influence a current through the resistor such that an output voltage of the level converter circuit does not exceed a maximum allowable value.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of copending InternationalApplication No. PCT/EP2014/071086, filed Oct. 1, 2014, which isincorporated herein by reference in its entirety, and additionallyclaims priority from German Application No. 102013220100.1, filed Oct.2, 2013, which is also incorporated herein by reference in its entirety.

BACKGROUND OF THE INVENTION

Embodiments of the present invention relate to a level convertercircuit. Further embodiments relate to an input circuit with inputtransistors and a level converter circuit coupled to the inputtransistors. Further embodiments relate to a method for operating alevel converter circuit. Some embodiments relate to a level converterfor fast CMOS input circuits.

For realizing fast data transmission (of e.g. more than 1000 Mbit persecond) across lossy cables, increased transmission power isnecessitated. However, modern CMOS technologies have the limitation thatfast transistors (having a structural size of less than 90 nm) have alower dielectric strength. This is in particular critical for receivercircuits since here level conversion has to be performed, which can, athigh signal levels (of e.g. more than 1V), no longer be realized withfast transistors.

Two solutions for solving this problem are known. According to a firstsolution, high input voltages are completely avoided, such that fasttransistors can be used. This results, however, in a reduction of thetransmission power or severely restricts the wirings that wouldotherwise be possible. According to a second solution, voltage-proof,slower transistors that perform a suitable level conversion are used forthe input stage. However, this restricts the maximum data rate.

Due to the low switching velocity of these transistors, the usage ofvoltage-proof transistors results in an input stage with lowamplification and bandwidth. On the one hand, this distorts the signalfurther, such that more measures for bandwidth compensation have to betaken, on the other hand, low amplification results in a poorersignal-to-noise ratio, since more amplifier stages are necessitated andmore noise is added at lower signal levels.

SUMMARY

According to a first embodiment, a level converter circuit may have: aninput with a first terminal and a second terminal; an output with athird terminal and a fourth terminal; a first resistor connected betweenthe first terminal and the third terminal; a second resistor connectedbetween the second terminal and the fourth terminal; and a currentadjustment circuit configured to influence a current through the firstresistor and a current through the second resistor such that an outputvoltage of the level converter circuit does not exceed a maximumallowable value; wherein the current adjustment circuit is a currentregulating circuit that is configured to regulate the current throughthe first resistor and the current through the second resistor based onthe output voltage; wherein the current level circuit includes a firsttransistor and a second transistor, wherein the first transistor isconfigured to influence the current through the first resistor, andwherein the second transistor is configured to influence the currentthrough the second resistor, wherein control voltages of the firsttransistor and the second transistor depend on the determined commonmode level of the output voltage; wherein the first transistor and thesecond transistor are field-effect transistors, and wherein the currentregulating circuit includes a common mode detector that is configured todetermine a common mode level of the output voltage, wherein the commonmode detector includes a voltage divider that is configured to providethe common mode level of the output voltage at a center of the voltagedivider, wherein gates of the field-effect transistors are connected tothe center of the voltage divider.

According to another embodiment, an input circuit may have: inputtransistors; and an inventive level converter circuit; wherein the inputtransistors are coupled to the output of the level converter circuit.

According to another embodiment, a method for operating a levelconverter circuit, wherein the level converter circuit includes an inputwith a first terminal and a second terminal, an output with a thirdterminal and a fourth terminal, a first resistor connected between thefirst terminal and the third terminal, a second resistor connectedbetween the second terminal and the fourth terminal, and a currentregulating circuit, wherein the current level circuit includes a firsttransistor and a second transistor, wherein the first transistor and thesecond transistor are field-effect transistors, wherein the currentregulating circuit includes a common mode detector that is configured todetermine a common mode level of the output voltage, wherein the commonmode detector includes a voltage divider, wherein gates of thefield-effect transistors are connected to the center of the voltagedivider, may have the steps of: influencing a current through the firstresistor and a current through the second resistor with the currentregulating circuit such that an output voltage of the level convertercircuit does not exceed a maximum allowable value; wherein, wheninfluencing the current through the first resistor and the currentthrough the second resistor, the current through the first resistor andthe current through the second resistor are regulated by the currentregulating circuit based on the output voltage; wherein the currentthrough the first resistor is influenced by the first transistor, andwherein the current through the second resistor is influenced by thesecond transistor; wherein control voltages of the first transistor andthe second transistor depend on the determined common mode level of theoutput voltage; wherein the common mode level of the output voltage isprovided at a center of the voltage divider.

Embodiments of the present invention provide a level converter circuitwith a resistor and a current adjustment circuit. The resistor isconnected between an input and an output of the level converter circuit.The current adjustment circuit is configured to influence a currentthrough the resistor such that an output voltage of the level convertercircuit does not exceed a maximum allowable value.

The present invention is based on the idea of performing levelconversion, e.g. from a high input level to a level acceptable for fasttransistors by means of a level converter circuit comprising a resistorand a current adjustment circuit, wherein the resistor is connectedbetween an input and an output of the level converter circuit, andwherein the current adjustment circuit is configured to influence acurrent through the resistor such that an output voltage of the levelconverter circuit does not exceed a maximum allowable value (e.g. alevel acceptable for fast transistors).

Further embodiments provide an input circuit with input transistors andthe above described level converter circuit. The level converter circuitcomprises a resistor and a current adjustment circuit. The resistor isconnected between an input and an output of the level converter circuit.The current adjustment circuit is configured to influence a currentthrough the resistor such that an output voltage of the level convertercircuit does not exceed a maximum allowable value. Here, the inputtransistors are coupled to the output of the level converter circuit.

Further embodiments provide a method for operating a level convertercircuit. The level converter circuit comprises a resistor and a currentadjustment circuit. The resistor is connected between an input and anoutput of the level converter circuit. The current adjustment circuit isconfigured to influence a current through the resistor such that anoutput voltage of the level converter circuit does not exceed a maximumallowable value. The method includes influencing a current through theresistor with the current adjustment circuit such that an output voltageof the level converter circuit does not exceed a maximum allowablevalue.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the present invention will be detailed subsequentlyreferring to the appended drawings, in which:

FIG. 1a is a schematic block diagram of a level converter circuitaccording to an embodiment of the present invention;

FIG. 1b is a schematic block diagram of a level converter circuitaccording to an embodiment of the present invention;

FIG. 2a is a schematic block diagram of a level converter circuitaccording to an embodiment of the present invention;

FIG. 2b is a schematic block diagram of a level converter circuitaccording to an embodiment of the present invention;

FIG. 2c is a schematic block diagram of a level converter circuitaccording to an embodiment of the present invention;

FIG. 3 is a schematic block diagram of an input circuit according to anembodiment of the present invention;

FIG. 4 is a flow diagram of a method for operating a level convertercircuit according to an embodiment of the present invention; and

FIG. 5 is a schematic block diagram of a measurement circuit.

DETAILED DESCRIPTION OF THE INVENTION

In the following description of the embodiments of the invention, equalor similar elements are provided with the same reference numbers in thefigures, such that their description is interchangeable in the differentembodiments.

FIG. 1a shows a schematic block diagram of a level converter circuit 10according to an embodiment of the present invention. The level convertercircuit 10 comprises a resistor 12 connected between an input 14 and anoutput 16 of the level converter circuit 10. Further, the levelconverter circuit 10 comprises a current adjustment circuit 18 that isconfigured to influence a current i through the resistor 12 such that anoutput voltage u_(out) of the level converter circuit 10 does not exceeda maximum allowable value.

In embodiments, the input 14 of the level converter circuit 10 cancomprise a first terminal 20 and a second terminal 22, while the output16 of the level converter circuit 10 can comprise a third terminal 24and a fourth terminal 26. Here, the resistor 12 can be connected betweenthe first terminal 20 and the third terminal 24. The second terminal 22and the fourth terminal 26 can each be connected to a referencepotential terminal 28, such as a ground terminal. An input voltageu_(in) can be applied between the first terminal 20 and the secondterminal 22, while the output voltage u_(out) can be applied between thethird terminal 24 and the fourth terminal 26.

In embodiments, the current adjustment circuit 18 can be a currentregulation circuit 18 that is configured to regulate the current ithrough the resistor 12 in dependence on the output voltage u_(out).

FIG. 1b shows a schematic block diagram of a level converter circuit 10according to an embodiment of the present invention. As can be seen inFIG. 1b , the current adjustment circuit 18 can comprise a transistor 30that is configured to influence the current i through the resistor 12.

The transistor 30 can be connected between an output side terminal ofthe resistor 12 or the output 16 (e.g. the third terminal 24) and areference potential terminal 28.

The current adjustment circuit 18 can, for example, be configured toprovide a control voltage u_(ct) for the transistor 30 such that thecontrol voltage u_(ct) of the transistor 30 depends on the outputvoltage u_(out).

FIG. 2a shows a schematic block diagram of a level converter circuit 10according to a further embodiment of the present invention. The levelconverter circuit 10 comprises the input 14 with the first terminal(e.g. positive input terminal) 20 and the second terminal (e.g. negativeinput terminal) 22, the output 16 with the third terminal (e.g. positiveoutput terminal) 24 and the fourth terminal (e.g. negative outputterminal) 26. Further, the level converter circuit 10 comprises thefirst resistor 12 connected between the first terminal 14 and the thirdterminal 24, and a second resistor 32 connected between the secondterminal 22 and the fourth terminal 26. Further, the level convertercircuit 10 comprises the current adjustment circuit 18 that isconfigured to influence the current i₁ through the first resistor 12 anda current i₂ through the second resistor 32 such that the output voltageu_(out) of the level converter circuit 10 does not exceed a maximumallowable value.

The current adjustment circuit 18 can be a current regulating circuit 18that is configured to regulate the current i₁ through the first resistor12 and the current i₂ through the second resistor 32 based on the outputvoltage u_(out).

FIG. 2b shows a level converter circuit 10 according to a furtherembodiment of the present invention. As can be seen in FIG. 2b , thecurrent adjustment circuit 18 can comprise a common mode detector 14that is configured to determine a common mode level of the outputvoltage u_(out) (applied between the third terminal 24 and the fourthterminal 26), wherein the current regulating circuit 18 is configured toregulate the current i₁ through the first resistor 12 (R1) and thecurrent i₂ through the second resistor 32 (R2) in dependence on thedetermined common mode level of the output voltage u_(out).

Further, the current regulating circuit 18 can comprise controllablecurrent or voltage sources 42 and 44 that are configured to influencethe current i₁ through the first resistor 12 (R1) and the current i₂through the second resistor 32 (R2). Here, the current regulatingcircuit 18 can be configured to control a nominal value of thecontrollable current or voltage sources 42 and 44 in dependence on thedetermined common mode level of the output voltage u_(out).

For example, a first controllable current or voltage source 42 of thecontrollable current or voltage sources 42 and 44 can be connectedbetween an output side terminal of the first resistor 12 (R1) and areference potential terminal 28, while a second current or voltagesource 44 of the controllable current or voltage sources 42 and 44 canbe connected between an output side terminal of the second resistor 32(R2) and the reference potential terminal 28.

Further, the current regulating circuit 18 can comprise an operationalamplifier 46, wherein a first input (e.g. positive input) of theoperational amplifier 46 can be connected to the common mode detector 40to obtain the common mode level of the output voltage u_(out) determinedby the common mode detector 40, wherein a second input (e.g. negativeinput) of the operational amplifier 46 can obtain a nominal voltageu_(nominal), which is provided, for example, externally or by thecurrent adjustment circuit 18, and wherein an output of the operationalamplifier 46 can be connected to control inputs of the controllablecurrent or voltage sources 42 and 44 to control the controllable currentor voltage sources 42 and 44.

The level converter circuit 10 enables lowering of the input level to alevel acceptable for the fast transistors without having to usevoltage-proof slow transistors. For this, a resistor 12 or 32 is usedthrough which a (constant or almost constant) current i₁ and i₂ flows inorder to generate a defined voltage drop. It should be noted that thecurrents i₁ and i₂ can really (slightly) vary. Further, it can beensured that the currents i₁ and i₂ generate a sufficient voltage drop,such that the input transistors are still within a secure operatingrange even when the operating voltage is not yet applied to thereceiver, but the transmitting counterpart is already active.

FIG. 2c shows a schematic block diagram of the level converter circuit10 according to an embodiment of the present invention. As can be seenin FIG. 2c , the common mode detector 40 of the current adjustmentcircuit 18 can comprise a voltage divider 40 that is configured toprovide the common mode level of the output voltage u_(out).

The voltage divider can comprise a third resistor 46 (R3) and a fourthresistor 48 (R4) that are connected between the third terminal 24 andthe fourth terminal 26. The common mode detector 40 can be configured toprovide the common mode level of the output voltage u_(out) at a node 50between the third resistor 46 and the fourth resistor 48.

Here, a resistance of the first resistor 12 (R1) can be lower than aresistance of the third resistor 46 (R3) by at least a factor of 2,while a resistance of the second resistor 32 (R2) can be lower than aresistance of the fourth resistor 48 (R4) by at least a factor of 2.

The current regulating circuit 18 can comprise a first transistor 30(M1) and a second transistor 52 (M2), wherein the first transistor 30can be configured to influence the current i₁ through the first resistor12 (R1), and wherein the second transistor 52 (M2) can be configured toinfluence the current i₂ through the second resistor 32 (R2), whereincontrol voltages of the first transistor 30 (M1) and the secondtransistor 52 (M2) depend on the determined common mode level of theoutput voltage u_(out).

Here, the first transistor 30 (M1) can be connected between an outputside terminal of the first resistor 12 (R1) or the third terminal 24 anda reference potential terminal 28, wherein the second transistor 52 (M2)can be connected between an output side terminal of the second resistor32 (R2) or the fourth terminal 26 and a reference potential terminal 28.

The first transistor 30 (M1) and the second transistor 52 (M2) can befield-effect transistors.

Here, gates of the field-effect transistors 30 (M1) and 52 (M2) can bepassively coupled, such that control voltages at the gates of thefield-effect transistors 30 (M1) and 52 (M2) are based exclusively on aninput voltage u_(in) of the level converter circuit 10.

As has already been mentioned, the current regulating circuit 18 cancomprise a common mode detector 40 that is configured to determine acommon mode level of the output voltage u_(out), wherein the common modedetector 40 can comprise a voltage divider that is configured to providethe common mode level of the output voltage u_(out) at a center 50 ofthe voltage divider. Here, gates of the field-effect transistors 30 (M1)and 52 (M2) can be connected to the center 50 of the voltage divider.

In other words, FIG. 2c shows the basic structure of the level convertercircuit 10 with transistors 30 (M1) and 52 (M2). The necessitated DCvoltage drops in a current controlled manner across resistors 12 and 32(R1 and R2). The resistors 46 and 48 (R3 and R4) detect the common modelevel by generating, as resistive dividers, an average voltage betweenthe third terminal 24 (e.g. positive output terminal) and the fourthterminal 26 (e.g. negative output terminal). This voltage serves asnominal quantity for the transistors 30 and 52 (M1 and M2), which draw aDC current from the resistors 12 and 32 (R1 and R2) and realize leveladaptation. The level converter circuit 10 has no terminal for explicitoperating voltage and hence also operates when no supply voltage isapplied. It is also possible that the control voltage is controlled bymore complex regulations/networks in a more fine-tuned manner in orderto be able to cover an even greater input range.

In embodiments, a gate width/gate length of the transistors 30 and 52(M1 and M2) can be selected such that the nominal voltage U_(nominal) atthe gates generates currents (e.g. drain current) generating thenecessitated voltage drops across the resistors 12 and 32 (R1 and R2).Otherwise, the transistors 30 and 52 (M1 and M2) are independent of thesuccessive input transistors. Here, it can be advantageous to select thegate length of transistors 30 and 52 (M1 and M2) as large as possibleand the gate width of the transistors 30 and 52 (M1 and M2) as small aspossible for reducing the capacitive load and for increasing theinternal resistor of the current source.

FIG. 3 shows a schematic block diagram of an input circuit 80 accordingto an embodiment of the present invention. The input circuit 80comprises input transistors 82 and 84 and the level converter circuit10. As can be seen in FIG. 3, the input transistors 82 and 84 can becoupled to the output 16 of the level converter circuit 10.

In embodiments, the input transistors 82 and 84 can be coupled directlyto the output 16 of the level converter circuit 10. More accurately, afirst input transistor 82 of the input transistors 82 and 84 can beconnected to the third terminal 24, while a second input transistor 84of the input transistors 82 and 84 can be connected to the fourthterminal 26 of the level converter circuit 10.

FIG. 4 shows a flow diagram of a method 100 for operating the levelconverter circuit 10 according to an embodiment of the presentinvention. The method 100 includes influencing 102 a current through theresistor with the current regulating circuit such that an output voltageof the level converter circuit does not exceed a maximum allowablevalue.

Embodiments of the present invention provide an alternative levelconverter 10 realizing the voltage drop at a resistor 12 and 32 andallowing level conversion without usage of a slow transistor and hencewithout reduction of bandwidth and amplification.

The level converter circuit 10 has the advantage of a large common moderange, low bandwidth loss or good amplification of the input stage andprotection of the sensitive input stage even without active operatingvoltage.

FIG. 5 shows a schematic block diagram of a measurement circuit 120. Themeasurement circuit 120 includes the level circuit 10, which comprises afirst resistor 12 (RL1) connected between a first terminal 20 and athird terminal 24, a second resistor 32 (RL2) connected between a secondterminal 22 and a fourth terminal 26, a voltage divider with a thirdresistor 46 (RC1) and a fourth resistor 48 (RC2) connected between thethird terminal 24 and the fourth terminal 26, a first controlled currentsource 30 connected between the third terminal 24 and a referencepotential terminal 28, and a second controlled current source 52connected between the fourth terminal 26 and the reference potentialterminal 28.

Further, the measurement circuit 120 comprises a fifth resistor 122(RT1) connected between the first terminal 20 and a reference potentialterminal 28 and a sixth resistor 124 (RT2) connected between the secondterminal 22 and a reference potential terminal 28. Further, themeasurement circuit 120 comprises a first current source 126 connectedbetween the first terminal 20 and a reference potential terminal 28 anda second current source 128 connected between the second terminal 22 anda reference potential terminal 28. Above that, the measurement circuit120 comprises a first voltage meter 130 connected between the firstterminal 20 and a reference potential terminal 28 and a second voltagemeter 132 connected between the second terminal 22 and a referencepotential terminal 28.

Since the circuit draws current directly from the termination resistors122 and 124 (RT1 and RT2), the voltage drop at these resistors cansimply be measured per multimeter 130 and 132 in dependence on aimpressed current which indicates a direct mode voltage at the input. 11and 12 have to be identical. In the level converter circuit, thecharacteristic line of fed-in Ito measured U shows significantnonlinearities, whereas conventional input stages show linear relations.

While some aspects have been described in the context of an apparatus,it is obvious that these aspects also represent a description of therespective method, such that a block or device of an apparatus can alsobe considered as a respective method step or as a feature of a methodstep. Analogously, aspects that have been described in the context ofone or as a method step also represent a description of a respectiveblock or detail or feature of a respective apparatus. Some or all of themethod steps can be performed by a hardware device (or by using ahardware device) such as a microprocessor, a programmable computer or anelectronic circuit. In some embodiments, some or all of the mostimportant method steps can be performed by such an apparatus.

While this invention has been described in terms of several advantageousembodiments, there are alterations, permutations, and equivalents whichfall within the scope of this invention. It should also be noted thatthere are many alternative ways of implementing the methods andcompositions of the present invention. It is therefore intended that thefollowing appended claims be interpreted as including all suchalterations, permutations, and equivalents as fall within the truespirit and scope of the present invention.

The invention claimed is:
 1. A level converter circuit, comprising: aninput with a first terminal and a second terminal; an output with athird terminal and a fourth terminal; a first resistor connected betweenthe first terminal and the third terminal; a second resistor connectedbetween the second terminal and the fourth terminal; and a currentadjustment circuit configured to influence a current through the firstresistor and a current through the second resistor such that an outputvoltage of the level converter circuit does not exceed a maximumallowable value; wherein the current adjustment circuit is a currentregulating circuit that is configured to regulate the current throughthe first resistor and the current through the second resistor based onthe output voltage; wherein the current regulating circuit comprises afirst transistor and a second transistor, wherein the first transistoris configured to influence the current through the first resistor, andwherein the second transistor is configured to influence the currentthrough the second resistor, wherein control voltages of the firsttransistor and the second transistor depend on the determined commonmode level of the output voltage; wherein the first transistor and thesecond transistor are field-effect transistors, and wherein the currentregulating circuit comprises a common mode detector that is configuredto determine a common mode level of the output voltage, wherein thecommon mode detector comprises a voltage divider that is configured toprovide the common mode level of the output voltage at a center of thevoltage divider, wherein gates of the field-effect transistors areconnected to the center of the voltage divider.
 2. The level convertercircuit according to claim 1, wherein the voltage divider comprises athird resistor and a fourth resistor that are connected between thethird terminal and the fourth terminal, wherein the common mode detectoris configured to provide the common mode level of the output voltage ata node between the third resistor and the fourth resistor.
 3. The levelconverter circuit according to claim 2, wherein a resistance of thefirst resistor is lower than a resistance of the third resistor by atleast a factor of two and wherein a resistance of the second resistor islower than a resistance of the fourth resistor by at least a factor oftwo.
 4. The level converter circuit according to claim 1, wherein thecurrent regulating circuit comprises controllable current or voltagesources that are configured to influence the current through the firstresistor and the current through the second resistor, wherein thecurrent regulating circuit is configured to control a nominal value ofthe controllable current or voltage sources in dependence on thedetermined common mode level of the output voltage.
 5. The levelconverter circuit according to claim 1, wherein the first transistor isconnected between an output side terminal of the first resistor or thethird terminal and a reference potential terminal, and wherein thesecond transistor is connected between an output side terminal of thesecond resistor or the fourth terminal and the reference potentialterminal.
 6. The level converter circuit according to claim 1, whereingates of the field-effect transistors are passively coupled, such thatcontrol voltages at the gates of the field-effect transistors are basedexclusively on an input voltage of the level converter circuit.
 7. Aninput circuit comprising: input transistors; and the level convertercircuit according to claim 1; wherein the input transistors are coupledto the output of the level converter circuit.
 8. The input circuitaccording to claim 7, wherein the input transistors are directly coupledto the output of the level converter circuit.
 9. Method for operating alevel converter circuit, wherein the level converter circuit comprisesan input with a first terminal and a second terminal, an output with athird terminal and a fourth terminal, a first resistor connected betweenthe first terminal and the third terminal, a second resistor connectedbetween the second terminal and the fourth terminal, and a currentregulating circuit, wherein the current regulating circuit comprises afirst transistor and a second transistor, wherein the first transistorand the second transistor are field-effect transistors, wherein thecurrent regulating circuit comprises a common mode detector that isconfigured to determine a common mode level of the output voltage,wherein the common mode detector comprises a voltage divider, whereingates of the field-effect transistors are connected to the center of thevoltage divider, wherein the method comprises: influencing a currentthrough the first resistor and a current through the second resistorwith the current regulating circuit such that an output voltage of thelevel converter circuit does not exceed a maximum allowable value;wherein, when influencing the current through the first resistor and thecurrent through the second resistor, the current through the firstresistor and the current through the second resistor are regulated bythe current regulating circuit based on the output voltage; wherein thecurrent through the first resistor is influenced by the firsttransistor, and wherein the current through the second resistor isinfluenced by the second transistor; wherein control voltages of thefirst transistor and the second transistor depend on the determinedcommon mode level of the output voltage; wherein the common mode levelof the output voltage is provided at a center of the voltage divider.